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| DS2164Q G.726 ADPCM Processor www.dalsemi.com FEATURES Compresses/expands 64kbps PCM voice to/from either 32 kbps, 24 kbps, or 16 kbps as per the CCITT/ITU G.726 specification Dual, fully independent channel architecture; device can be programmed to perform either: - two expansions - two compressions - one expansion and one compression Interconnects directly to combo-codec devices Input to output delay is less than 375 s Simple serial port used to configure the device Onboard Time Slot Assigner Circuit (TSAC) function allows data to be input/output at various time slots Supports Channel Associated Signaling Each channel can be independently idled or placed into bypass Available hardware mode requires no host processor; ideal for voice storage applications Backward-compatible with the DS2165 ADPCM Processor Chip Single +5V supply; low-power CMOS technology Available in 28-pin PLCC PIN ASSIGNMENT TM1 TM0 RST NC VDD YIN CLKY NC A0 A1 A2 A3 A4 A5 5 6 7 8 9 10 11 12 4 3 2 1 28 27 26 25 24 23 22 21 20 19 13 14 15 16 17 18 FSY YOUT CS SDI SCLK XOUT NC DESCRIPTION The DS2164Q ADPCM Processor Chip is a dedicated Digital Signal Processing (DSP) chip that has been optimized to perform Adaptive Differential Pulse Code Modulation (ADPCM) speech compression at three different rates. The chip can be programmed to compress (expand) 64kbps voice data down to (up from) either 32kbps, 24kbps, or 16kbps. The compression follows the algorithm specified by CCITT Recommendation G.726. The DS2164Q can switch compression algorithms on-the-fly. This allows the user to make maximum use of the available bandwidth on a dynamic basis. OVERVIEW The DS2164Q contains three major functional blocks: a high performance (10 MIPS) DSP engine, two independent PCM interfaces (X and Y) which connect directly to serial Time Division Multiplexed (TDM) backplanes, and a serial port that can configure the device on-the-fly via an external controller. A 1 of 17 112099 SPS MCLK VSS NC XIN CLKX FSX 28-Pin PLCC DS2164Q 10 MHz master clock is required by the DSP engine. The DS2164Q can be configured to perform either two expansions, two compressions, or one expansion and one compression. The PCM/ADPCM data interfaces support data rates from 256 kHz to 4.096 MHz. Typically, the PCM data rates will be 1.544 MHz for -law and 2.048 MHz for A-law. Each channel on the device samples the serial input PCM or ADPCM bit stream during a user-programmed input time slot, processes the data and outputs the result during a user-programmed output time slot. Each PCM interface has a control register which specifies functional characteristics (compress, expand, bypass, and idle), data format (-law or A-law), and algorithm reset control. With the SPS pin strapped high, the software mode is enabled and the serial port can be used to configure the device. In this mode, a novel addressing scheme allows multiple devices to share a common 3-wire control bus, simplifying system-level interconnect. With SPS low, the hardware mode is enabled. This mode disables the serial port and maps certain control register bits to some of the address and serial port pins. Under the hardware mode, no external host controller is required and all PCM/ADPCM input and output time slots default to time slot 0. HARDWARE RESET RST allows the user to reset both channel algorithms and the contents of the internal registers. This pin must be held low for at least 1 ms on system power-up after the master clock is stable to ensure that that the device has initialized properly. RST should also be asserted when changing to or from the hardware mode. RST clears all bits of the Control Register for both channels except the IPD bits; the IPD bits for both channels are set to 1. SOFTWARE MODE Tying SPS high enables the software mode. In this mode, an external host controller writes configuration data to the DS2164Q via the serial port through inputs SCLK, SDI, and CS . (See Figure 2.) Each write to the DS2164Q is either a 2-byte write or a 4-byte write. A 2-byte write consists of the Address/Command Byte (ACB), followed by a byte to configure the Control Register (CR) for either the X or Y channel. The 4-byte write consists of the ACB, followed by a byte to configure the CR, and then 1 byte to set the input time slot and another byte to set the output time slot. ADDRESS/COMMAND BYTE In the software mode, the address/command byte is the first byte written to the serial port; it identifies which of the 64 possible ADPCM processors sharing the port wiring is to be updated. Address data must match that at inputs A0 to A5. If no match occurs, the device ignores the following configuration data. If an address match occurs, the next 3 bytes written are accepted as control, input and output time slot data. Bit ACB.6 determines which side (X or Y) of the device is to be updated. The PCM and ADPCM outputs are tristated during register updates. CONTROL REGISTER The control register establishes idle, algorithm reset, bypass, data format and channel coding for the selected channel. The X and Y side PCM interfaces can be independently disabled (output 3-stated) via IPD. When IPD is set for both channels, the device enters a low-power standby mode. In this mode, the serial port must not be operated faster than 39 kHz. ALRST resets the algorithm coefficients for the selected channel to their initial values. ALRST will be cleared by the device when the algorithm reset is complete. 2 of 17 DS2164Q PIN DESCRIPTION Table 1 PIN 2 SYMBOL RST TYPE I DESCRIPTION Reset. A high-low-high transition resets the algorithm. The device should be reset on power up and when changing to or from the hardware mode. Test Modes 0 and 1. Tie to VSS for normal operation. Address Select. A0 = LSB; A5 = MSB Must match address/command word to enable the serial port. 3 4 6 7 8 9 10 11 12 13 14 16 17 18 20 21 22 23 24 25 26 27 28 TM0 TM1 A0 A1 A2 A3 A4 A5 SPS MCLK VSS XIN CLKX FSX XOUT SCLK SDI CS I I I I I I I O I I I O I I I - Serial Port Select. Tie to VDD to select the serial port; tie to VSS to select the hardware mode. Master Clock. 10 MHz clock for the ADPCM processing engine; may be asynchronous to SCLK, CLKX, and CLKY. Signal Ground. 0.0 volts. X Data In. Sampled on falling edge of CLKX during selected time slots. X Data Clock. Data clock for the X side PCM interface; must be synchronous with FSX. X Frame Sync. 8 kHz frame sync for the X side PCM interface. X Data Output. Updated on rising edge of CLKX during selected time slots. Serial Data Clock. Used to write to the serial port registers. Serial Data In. Data for onboard control registers; sampled on the rising edge of SCLK. LSB sent first. Chip Select. Must be low to write to the serial port. Y Data Output. Updated on rising edge of CLKY during selected time slots. Y Frame Sync. 8 kHz frame sync for the Y side PCM interface. Y Data Clock. Data clock for the Y side PCM interface; must be synchronous with FSY. Y Data In. Sampled on falling edge of CLKY during selected time slots. Positive Supply. 5.0 volts. YOUT FSY CLKY YIN VDD 3 of 17 DS2164Q DS2164Q BLOCK DIAGRAM Figure 1 SERIAL PORT WRITE Figure 2 NOTE: 1. A 2-byte write is shown. The bypass feature is enabled when BYP is set and IPD is cleared. During bypass, no expansion or compression occurs. Bypass operates on bytewide (8 bits) slots when CP/ EX is set and on nibble-wide (4 bits) slots when CP/ EX is cleared. A-law (U/ A = 0) and -law (U/ A = 1) PCM coding is independently selected for the X and Y channels via CR.2. If BYP and IPD are cleared, then CP/ EX determines if the input data is to be compressed or expanded. 4 of 17 DS2164Q ADDRESS/COMMAND BYTE Figure 3 (MSB) X/ Y A5 POSITION ACB.7 ACB.6 A4 A3 A2 A1 (LSB) A0 SYMBOL X/ Y NAME AND DESCRIPTION Reserved; must be 0 for proper operation X/Y Channel Select 0 = update channel Y characteristics 1 = update channel X characteristics MSB of Device Address A5 A4 A3 A2 A1 A0 ACB.5 ACB.4 ACB.3 ACB.2 ACB.1 ACB.0 LSB of Device Address CONTROL REGISTER Figure 4 (MSB) AS0 (LSB) AS1 IPD POSITION CR.7 CR.6 CR.5 ALRST BYP U/ A AS2 CP/ EX SYMBOL AS0 AS1 IPD NAME AND DESCRIPTION Algorithm Select 0. See Table 2. Algorithm Select 1. See Table 2. Idle and Power Down. 0 = channel enabled 1 = channel disabled (output 3-stated) Algorithm Reset. 0 = normal operation 1 = reset algorithm for selected channel Bypass. 0 = normal operation 1 = bypass selected channel Data Format. 0 = A-law 1 = -law Algorithm Select 2. See Table 2. Channel Coding. 0 = expand (decode) selected channel 1 = compress (encode) selected channel ALRST CR.4 BYP CR.3 U/ A CR.2 AS2 CP/ EX CR.1 CR.0 5 of 17 DS2164Q ALGORITHM SELECT BITS Table 2 ALGORITHM SELECTED 64kbps to/from 32 kbps 64kbps to/from 24 kbps 64kbps to/from 16 kbps AS2 0 1 1 AS1 0 1 0 AS0 0 1 1 INPUT TIME SLOT REGISTER Figure 5 (MSB) D5 POSITION ITR.7 ITR.6 ITR.5 ITR.4 ITR.3 ITR.2 ITR.1 ITR.0 LSB of input time slot register. D4 D3 D2 D1 (LSB) D0 SYMBOL D5 D4 D3 D2 D1 D0 NAME AND DESCRIPTION Reserved; must be 0 for proper operation. Reserved; must be 0 for proper operation. MSB of input time slot register. OUTPUT TIME SLOT REGISTER Figure 6 (MSB) D5 POSITION OTR.7 OTR.6 OTR.5 OTR.4 OTR.3 OTR.2 OTR.1 OTR.0 LSB of output time slot register. D4 D3 D2 D1 (LSB) D0 SYMBOL D5 D4 D3 D2 D1 D0 NAME AND DESCRIPTION Reserved; must be 0 for proper operation. Reserved; must be 0 for proper operation. MSB of output time slot register. 6 of 17 DS2164Q TIME SLOT ASSIGNMENT/ORGANIZATION Onboard counters establish when PCM and ADPCM I/O occur. The counters are programmed via the time slot registers. Time slot size (number of bits wide) is determined by the state of CP/ EX . The number of time slots available is determined by the state of both CP/ EX and U/ A . (See Figures 7 through 10.) For example, if the X channel is set to compress (CP/ EX = 1) and it is set to expect -law data (U/ A = 1), then the input port (XIN) is set up for 32 8-bit time slots and the output port (XOUT) is set up for 64 4-bit time slots. The time slot organization is not dependent on which algorithm has been selected. NOTE: Time slots are counted from the frame sync signal starting at the first rising edge of either CLKX or CLKY after the frame sync. DS2164Q -LAW PCM INTERFACE Figure 7 DS2164Q -LAW ADPCM INTERFACE Figure 8 7 of 17 DS2164Q DS2164Q A-LAW PCM INTERFACE Figure 9 DS2164Q A-LAW ADPCM INTERFACE Figure 10 8 of 17 DS2164Q HARDWARE MODE The hardware mode is intended for applications that do not have an external controller available or do not require the extended features offered by the serial port. Tying the SPS pin to VSS disables the serial port, clears all internal register bits and maps the IPD, U/ A , and CP/ EX bits for both channels to external bits. (See Table 3.) In the hardware mode, both the input and output time slots default to time slot 0. HARDWARE MODE Table 3 PIN # / NAME 4 / A0 REG. LOCATION CP/ EX (Channel X) AS0/AS1/AS2 (Channel X & Y) U/ A (Channel X) CP/ EX (Channel Y) AS0/AS1/AS2 (Channel X & Y) U/ A (Channel Y) IPD (Channel Y) IPD (Channel X) NAME AND DESCRIPTION Channel X Coding Configuration 0 = Expand 1 = Compress Algorithm Select (see Table 5) Channel X Data Format 0 = A-law 1 = -law Channel Y Coding Configuration 0 = Expand 1 = Compress Algorithm Select (see Table 5) Channel Y Data Format 0 = A-law 1 = -law Channel Y Idle Select 0 = Channel active 1 = Channel idle Channel X Idle Select 0 = Channel active 1 = Channel idle 5 / A1 6 / A2 7 / A3 8 / A4 9 / A5 18 / SDI 19 / CS NOTES: 1. SCLK must be tied to VSS when the hardware mode is selected. 2. When both channels are idled, power consumption is significantly reduced. 3. The DS2164Q will power-up within 800 ms after either channel is returned to active from an idle state. 9 of 17 DS2164Q ALGORITHM SELECT FOR HARDWARE MODE Table 4 ALGORITHM 64kbps to/from 32kbps 64kpbs to/from 24kbps CONFIGURATION OF A1 AND A4 Tie both A1 and A4 to VSS. Hold A1 and A4 low during a hardware reset; take both A1 and A4 high after the RST pin has returned high (allow 3 s after RST returns high before taking A1 and A4 high). Tie both A1 and A4 to VDD. 64kbps to/from 16kbps DS2164Q CONNECTION TO CODEC/FILTER Figure 11 NOTE: Suggested Codec/Filters TP305X National Semiconductor ETC505X SGS-Thomson Microelectronics MC1455XX Motorola TCM29CXX Texas Instruments HD44238C Hitachi *other generic Codec/Filter devices can be substituted. 10 of 17 DS2164Q PCM AND ADPCM INPUT/OUTPUT Since the organization of the input and output time slots on the DS2164Q does not depend on the algorithm selected, it always assumes that PCM input and output will be in 8-bit bytes and that ADPCM input and output will be in 4-bit bytes. Figure 12 demonstrates how the DS2164Q handles the I/O for the three different algorithms. In the figure, it is assumed that channel X is in the compression mode (CP/ EX = 1) and channel Y is in the expansion mode (CP/ EX = 0). Also, it is assumed that both the input and output time slots for both channels are set to 0. PCM AND ADPCM I/O EXAMPLE Figure 12 NOTE: 1. The bit after the LSB in the 24 kbps ADPCM output will only be a 1 when the DS2164Q is operated in the software mode and is programmed to perform 24 kbps compression; in all other configurations, it will be a 0. 11 of 17 DS2164Q TIME SLOT RESTRICTIONS Under certain conditions, the DS2164Q does contain some restrictions on the output time slots that are available. These restrictions are covered in detail in a separate application note. No restrictions occur if the DS2164Q is operated in the hardware mode. INPUT TO OUTPUT DELAY With all three compressions algorithms, the total delay, from the time the PCM data sample is captured by the DS2164Q to the time it is output, is always less than 375 s. The exact delay is determined by the input and output time slots selected for each channel. CHANNEL ASSOCIATED SIGNALING The DS2164Q supports Channel Associated Signaling (CAS) via its ability to automatically change from the 32 kbps compression algorithm to the 24 kbps algorithm. If the DS2164Q is configured to perform the 32kbps algorithm, then in both the hardware and software mode, it will sense the frame sync inputs (FSX and FSY) for a double-wide frame sync pulse. Whenever the DS2164Q receives a double-wide pulse, it will automatically switch from the 32kbps algorithm to the 24kbps algorithm. Switching to the 24 kbps algorithm allows the user to insert signaling data into the LSB bit position of the ADPCM output because this bit does not contain any useful speech information. ON-THE-FLY ALGORITHM SELECTION In the software mode, the user can switch between the three available algorithms on-the-fly. That is, the DS2164Q does not need to be reset or stopped to make the change from one algorithm to another. The DS2164Q reads the Control Register before it starts to process each PCM or ADPCM sample. If the user wishes to switch algorithms, then the Control Register must be updated via the serial port before the first input sample to be processed with the new algorithm arrives at either XIN or YIN. The PCM and ACPCM outputs will tristate during register updates. 12 of 17 DS2164Q ABSOLUTE MAXIMUM RATINGS* Voltage on any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature * -1.0V to +7.0V 0C to 70C -55C to +125C 260C for 10 seconds This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. RECOMMENDED DC OPERATING CONDITIONS PARAMETER Logic 1 Logic 0 Supply SYMBOL VIH VIL VDD MIN 2.0 -0.3 4.5 TYP MAX VCC+0.3 +0.8 5.5 (0C to 70C) UNITS V V V NOTES CAPACITANCE PARAMETER Input Capacitance Output Capacitance SYMBOL CIN COUT MIN TYP MAX 5 10 (tA =25C) UNITS pF pF NOTES DC ELECTRICAL CHARACTERISTICS PARAMETER Active Supply Current Idle Supply Current Input Leakage Output Leakage Output Current (2.4V) Output Current (0.4V) SYMBOL IDDA IDDPD II IO IOH IOL -1.0 -1.0 -1.0 +4.0 MIN (0C to 70C; VDD=5V 10%) TYP 20 1 +1.0 +1.0 MAX UNITS mA mA A A mA mA 4 NOTES 1, 2 1, 2, 3 NOTES: 1. CLKX = CLKY = 1.544 MHz; MCLK = 10 MHz. 2. Outputs open; inputs swinging full supply levels. 3. Both channels in idle mode. 4. XOUT and YOUT are 3-stated. 13 of 17 DS2164Q PCM INTERFACE AC ELECTRICAL CHARACTERISTICS PARAMETER CLKX, CLKY Period CLKX, CLKY Pulse Width CLKX, CLKY Rise Fall Times Hold Time from CLKX, CLKY to FSX, FSY Setup Time from FSX, FSY High to CLKX, CLKY Low Hold Time from CLKX, CLKY Low to FSX, FSY Low Setup Time for XIN, YIN to CLKX, CLKY Low Hold Time for XIN, YIN to CLKX, CLKY Low Delay Time from CLKX, CLKY to Valid XOUT, YOUT Delay Time from CLKX, CLKY to XOUT, YOUT 3-stated SYMBOL tPXY tWXYL tWXYH tRXY tFXY tHOLD tSF tHF tSD tHD tDXYO tDXYZ 0 50 100 50 50 10 20 MIN 244 100 (0C to 70C; VDD=5V 10%) TYP MAX 3906 UNITS ns ns 10 20 ns ns ns ns ns ns 150 150 ns ns 2 2 2 2 2 3 2, 3, 4 NOTES 1 NOTES: 1. Maximum width of FSX and FSY is one CLKX or CLKY period (except for signaling frames). 2. Measured at VIH = 2.0V, VIL = 0.8V, and 10 ns maximum rise and fall times. 3. Load = 150 pF + 2 LSTTL loads. 4. For LSB of PCM or ADPCM byte. MASTER CLOCK / RESET AC ELECTRICAL CHARACTERISTICS PARAMETER MCLK Period MCLK Pulse Width MCLK Rise/Fall Times RST (0C to 70C; VDD=5V 10%) MIN 45 TYP 100 50 MAX 55 10 1 UNITS ns ns ns ms NOTES 1 SYMBOL tPM tWMH, tWML tRM, tFM tRST Pulse Width NOTE: 1. MCLK = 10 MHz 500 ppm 14 of 17 DS2164Q SERIAL PORT AC ELECTRICAL CHARACTERISTICS PARAMETER SDI to SCLK Set Up SCLK to SDI Hold SCLK Low Time SCLK High Time SCLK Rise and Fall Time CS to SCLK Setup SCLK to CS Hold CS Inactive Time SCLK Setup to CS Falling SYMBOL tDC tCDH tCL tCH t R , tF tCC tCCH tCWH tSCC 50 250 250 50 MIN 55 55 250 250 (0C to 70C; VDD=5V 10%) TYP MAX UNITS ns ns ns ns 100 ns ns ns ns ns NOTES 1 1 1 1 1 1 1 1 1 NOTE: 1. Measured at VIH = 2.0V, VIL = 0.8V, and 10ns maximum rise and fall times. PCM INTERFACE AC TIMING DIAGRAM Figure 13 15 of 17 DS2164Q MASTER CLOCK/RESET AC TIMING DIAGRAM Figure 14 SERIAL PORT AC TIMING DIAGRAM Figure 15 NOTE: 1. SCLK may be either high or low when CS is taken low. 16 of 17 DS2164Q DS2164Q G.726 ADPCM PROCESSOR 28-PIN PLCC INCHES DIM A A1 A2 B B1 C D D1 D2 E E1 E2 L1 N e1 CH1 MIN 0.165 0.090 0.020 0.026 0.013 0.009 0.485 0.450 0.390 0.485 0.450 0.390 0.060 28 MAX 0.180 0.120 0.033 0.021 0.012 0.495 0.456 0.430 0.495 0.456 0.430 - 0.050 BSC 0.042 0.048 17 of 17 |
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